This application claims the priority of Korean Patent Application No. 2004-0085800, filed on Oct. 26, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a programming method for setting a phase-change memory array and a semiconductor memory device implementing the programming method.
2. Description of the Related Art
PRAMs (Phase-change Random Access Memories) are non-volatile memory devices for storing data using a material (hereinafter, referred to as phase-change material), such as GST (Ge—Sb—Te), whose resistance changes according to a change of phase of the material. PRAMs, which are non-volatile, can achieve low power consumption as well as having all the advantages of DRAMs. When data is written to a PRAM, a current flows in a phase-change material and the phase-change material changes to a crystalline state or to an amorphous state, depending upon the amplitude and duration of the current That is, whether the phase-change material changes to a crystalline state or an amorphous state depends on the amplitude and duration of current flowing through the phase-change material. amorphous state, which is generally called a reset state corresponding to data value of “1”.
If a current having an amplitude smaller than the reset current flows through the phase-change material for a long time period, the phase-change material changes to the crystalline state, which is generally called a set state corresponding to data of “0”.
The resistance of the phase-change material is greater in the reset state than in the set state. An initial set state of a memory cell is changed to a reset state by passing a reset current through the phase-change material to heat the phase-change material above a melting temperature and then quickly cooling the phase-change material.
On the other hand an initial reset state of a memory cell is changed to a set state by passing a set current through the phase-change material to heat the phase-change material above a crystallization temperature, maintaining the phase-change material at the temperature for a predetermined time, and then cooling the phase-change material.
FIG. 1A shows exemplary current pulses for writing data in a phase-change material.
Referring to FIG. 1A, by applying a short, large current pulse I_RESET to the phase-change material, melting the phase-change material, and then quickly cooling the phase-change material, the phase-change material is changed to an amorphous state (reset state). Conversely, by applying a long, small current pulse I_SET to the phase-change material and heating the phase-change material above a crystallization temperature, the phase-change material is changed to a crystalline state (set state).
However, in a memory array including a plurality of phase-change memory cells, the parasitic resistances of the memory cells can be different from each other according to the arrangement of the memory cells in the memory array.
Also, the loads on signal lines connected respectively to the memory cells can be different from each other and the respective memory cells can have different reset currents due to variations in of the memory array area. The difference in the reset currents of the memory cells causes a difference in set currents. As such, since, in a memory cell array including a plurality of phase-change cells, set currents for changing the respective phase-change cells to a set state are different from each other, it is impossible to change all memory cells to a set state using a constant set current.
That is, while some memory cells change to a set state, the other memory cells may remain in a reset state. Or, some memory cells that are in the set state can have different resistances from those of the remaining memory cells that are in the set state. This can cause operating errors of the phase-change memory array.
FIGS. 1B through 1D show waveforms of various set current pulses that may be used to address the problems in set programming as described above with reference to FIG. 1A.
Accordingly, it would be desirable to provide a more effective circuit for generating the set current pulses shown in FIGS. 1B-1D. It would also be desirable to provide a phase-change semiconductor memory device capable of changing all memory cells of a phase-change memory array to a set state.
According to an aspect of the present invention, there is provided a semiconductor memory device including phase-change cells whose states transit to a reset resistance state or a set resistance state in response to an applied current pulse, comprising: a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein a minimum current amount of the first through n-th stages is larger than a reference current amount and current amounts of the first through n-th stages are sequentially reduced; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal. The set control signal is a voltage pulse having first through n-th stages whose minimum voltage is larger than a reference voltage and whose voltages are sequentially reduced.
The semiconductor memory device further comprises: an oscillator activated in response to an operation activation signal, outputting clock pulses in response to a pull-up control signal and a pull-down control signal; a shifter receiving the clock pulses and the operation activation signal and outputting the first through n-th control pulses in response to a shift control signal; and a set control circuit outputting the set control signal in response to the operation activation signal and the first through n-th control pulses.
In the oscillator, if a voltage level of the pull-up control signal rises or if a voltage level of the pull-down control signal falls down, a period of each clock pulse becomes longer.
The set control circuit comprises: a control node; a controller receiving the operation activation signal and controlling such that a voltage of the control node is sequentially reduced in response to the first through n-th control pulses; and a set control signal generator controlling a waveform of the set control signal output from the control node according to logic levels of mode control signals.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a set control circuit generating a set control signal in response to first through n-th control pulses each sequentially activated for each predetermined time such that activation times of the first through n-th pulses do not overlap to each other; a write driver generating a set current pulse in response to the set control signal while a set pulse width control signal is activated if write data is set data, and generating a reset current pulse while a reset pulse width control signal is activated if the write data is reset data, wherein the set current pulse has first through n-th stages whose minimum current amount is larger than a reference current amount and whose current amounts are sequentially reduced; and a pulse generation circuit generating the set pulse width control signal and the reset pulse width control signal in response to a write enable pulse indicating data writing and the first through n-th control pulses.